The handheld consumer products market is aggressive in the miniaturization of portable electronics. Driven primarily by the cellular phone and digital assistant markets, manufacturers of these devices are challenged by ever shrinking formats and the demand for more PC-like functionality. This challenge asserts pressure on surface mount component manufacturers to design their products to command the smallest area possible. By doing so, this allows portable electronics designers to incorporate additional functions within a device without increasing the overall product size.
Manufacturers have developed various types of package and interconnect technologies to reduce the overall size of semiconductor components. Examples of packaging technologies include leadless packages, surface mount packages, chip-scale packages, and ball grid array packages. Examples of representative interconnection technologies include flip-chip interconnects, which includes solder ball, solder bump, and stud bump interconnect structures.
In a typical device using flip-chip interconnects, aluminum pads are formed overlying a semiconductor chip. A nitride passivation layer is then formed overlying the chip, and an organic passivation layer such as a benzocyclobutene (BCB1) layer is formed overlying the nitride passivation layer. Openings are then formed in the BCB1 and nitride layers to expose the aluminum pads. Next, under bump metal (UBM) pads such as an AlNiVCu pads are formed within the openings and contacting the underlying and exposed aluminum pads. Solder bumps or balls are then attached to the UBM pads using soldering, ball bonding, or stud bumping techniques.
Several problems exist with the flip-chip interconnect processes described above including process variability and reliability issues associated with the dissimilar materials. Also, the process flow is complicated by the ball attach or bump processes. Additionally, the conventional flip-chip interconnect process is very expensive with costs in the range of $90 to $150 per 200 mm wafer.
Accordingly, a need exists for an improved electronic package structure and method that has a small size, that is cost effective, and that addresses the reliability problems associated with solder ball/bump interconnect schemes described above.